1. Field of the Invention
The present invention relates to semiconductor memories and, more particularly, to semiconductor memories controlled with access allow signal generation in response to an access request signal.
2. Brief Description of Related Prior Art
In a cache memory system capable of controlling access allow signal generation in response to the access request signal, the time until it is possible to output the data is different for cache hit operation and cache miss-hit judgment. Therefore, it is necessary to supply an access allow signal to an access controller for the cache memory to notify that it is or is not possible to use cache memory output data.
FIG. 6 is a block diagram showing a cache memory circuit. The operation of the cache memory system will now be described with reference to FIG. 6. The cache memory circuit comprises a main memory 8 which may be DRAM or the like having large memory capacity and relatively slow operation, a cache memory 9 capable of fast operation and for holding a copy of some of the data in the memory 8, a tag memory 12 capable of a fast memory operation and for holding the address data of the main memory 8 corresponding to the data held by the cache memory 9, a controller (not shown) for outputting address and control signals, an activating controller 13 for activating the tag memory 12 and the cache memory 9 according to received control signals, and a comparator 11 which receives part of input address data from the tag memory 12. The cache memory 9 also receives some address data. The comparator 11 compares the remaining input address bits and the output of the tag memory 12. When the two input data are in accord, a cache hit condition exists and a selector 10 generates the output of the cache memory 9 as the data output and also outputs an inverted access allow signal inversion RDY. Because of the use of fast memory operation, the data and inverted access allow signal RDY can be outputted in a short time from the instant of an access request.
When the output of the tag memory 12 fails to be in accord with the input address, it is judged as the cache miss. The memory 8 receives a non-accord signal from the comparator 11 and executes the accessing operation according to the input address to output the data to the selector 10. When the miss-hit judgment occurs, the selector 10 sends out the output data of the memory 8 to a data line (not shown). The data in the memory 8 is thus outputted as the output data. At the same time, the access allow signal (inverted RDY) is outputted in a timed relation to the data output from the memory 8. The cache memory 9 writes the data of the memory 8 that is read out from the same address, and the tug memory 12 writes the corresponding miss-hit address so as to be ready for the next access cycle. In the case of the miss-hit judgment, the data output and access allow signal are relatively slow as result of the access time of the memory 8. Thus, in connection with the data access time and access allow signal, the response time is different depending upon whether cache hit or cache miss-hit exists.
The write operation of this cache circuit will now be described. A write-back operation will be described, which requires an operation of holding the data in the cache memory 9 and main memory 8 in accord. In the write operation, the data are written in only the cache memory 9 at the cache hit time, thus curtailing the write cycle time. Since the data in the memory 8 have not been updated, the data in the memory 8 and cache memory 9 are different in the corresponding address.
In the event of miss-hit in the pertinent cache memory in a subsequent memory cycle, before writing the new data through erasing the data in the cache memory 9, the data in the cache memory 9 is written in the corresponding address of the memory 8, and the miss-hit data is accessed from the memory 8 for writing the data in the cache memory 9 and updating the data in the tag memory 12.
The data output in this case requires two memory cycles, and the access allow signal generation is greatly delayed. The memory including the above cache operation judging circuit requires four parallel devices in order to construct a 32-bit data bus in the case of 8 bit I/O.
The operation timing in which the write operation for single one of the parallel memories is executed, will now be described. Referring to FIG. 4, inverted memory select signal CS is inputted to memories 21 and 22. An address signal Add is also inputted to the memories 21 and 22. Inverted signal We1 is for writing data in the memory 21, and inverted signal We2 is for writing data in the memory 22. Inverted signal RDY1 is an access allow signal from an access allow signal generator 20 in the memory 21. Inverted signal RDY2 is an access allow signal from the access allow signal generator 20 in the memory 22. A NAND gate receives the inverted access allow signals RDY1 and RDY2 and provides an output thereof to the gate of an n-channel transistor 5. The transistor 5 has its source grounded, and provides inverted signal RDY from its gate through a resistor 3 to a power supply. When the inverted signal RDY is inverted to the low level, the memory can be accessed.
Operation will now be described with reference to the timing chart of FIG. 5. In memory cycle T1, the inverted memory select signal CS is activated to execute write operation for the memory 21. On the other hand, since the inverted write signal We2 is held inactive, no write operation is executed for the memory 22. In this cycle T1, the memories 21 and 22 are operated to generate the inverted access allow signals RDY1 and RDY2 substantially in the same timing. In the next memory cycle T2, the inverted memory select signal CS is activated. At this time, since the write operation has been executed for the memory 21 in the preceding cycle T1, a cache clear signal may be generated for the pertinent cache memory. In this case, after the activation of the inverted memory select signal CS a judgment as to whether the cache memory has been cleared is executed to execute writing operation of the write data in the memory cell and then accept allowance with respect to the address, to which the access request is generated. Therefore, the activation of the inverted allowed access signal RDY1 is delayed.
On the other hand, no write cycle has been executed for the memory 22, and the inverted access allow signal RDY2 is generated without delay due to the activation of the inverted memory select signal CS. In such a cycle, all the access allow signals generated from the memories in parallel operation are deviated. The memory access allowance, therefore, has to be timed to the latter one of the two signals.
This means that the NAND gate 4 shown in FIG. 4 has to take logic operation of the inverted access allow signal RDY1 and RDY2 before providing the access allow inverted signal RDY to signal line RDY, which is common to other devices, through a transistor 5. As for the inverted access allow signal RDY of the controller 42, the transistor 5 is arranged to provide an open-drain structure for wired OR of a plurality of access allow signals for devices other than memory (not shown).
However, where a plurality of semiconductor memory devices which have the above prior art signal input system and generate an access allow signal in response to an access request are operated in parallel, an extra external logic circuit is necessary for the access allow signals, and also a delay is produced in the access allow signal, for which the controller is required to provide the highest speed.